Field
Embodiments of the present invention generally relate to hardware virtualization in which a common translation mechanism may be used by multiple central processing units (CPUs) and devices coupled to a shared, partitioned memory via an interconnect matrix/bus. In particular, embodiments of the present invention facilitate heterogeneous integration of multiple, potentially proprietary, software applications/environments, by implementing hardware memory virtualization/translation so as to make it appear to each partitioned CPU of the system that their partition of memory is a continuous region starting from a predefined address or configurable base address despite the fact that the same physical memory is being shared by multiple CPUs.
Description of Related Art
Virtualization technologies are becoming prevalent in the market place. Some of the existing technologies provide a virtual hardware abstraction to guest operating systems, and allow them to run in virtual machines in a functionally isolated environment on a host computer without being modified. Virtualization allows one or more virtual (guest) machines to run on a single physical (host) computer, providing functional and performance isolation for processor, memory, storage, etc.
To permit computer systems to scale to larger numbers of concurrent threads, systems with multiple CPUs have been developed. Such multi-processor systems are available as extensions of the PC platform, or as other hardware architectures. Typically, such multi-processor systems connect multiple processors and shared Input/Output (I/O) devices to a shared main memory via an interconnect bus. Virtual machines may also be configured as multi-processor virtual machines. Yet another configuration is found in a so-called “multi-core” architecture, in which more than one physical CPU is fabricated on a single chip, with its own set of functional units (such as a floating-point unit and an arithmetic/logic unit (ALU)), and can execute threads independently; multi-core processors typically share only very limited resources such as some cache. Still another configuration that provides for simultaneous execution of multiple threads is referred to as “simultaneous multi-threading,” in which more than one logical CPU (hardware thread) operates simultaneously on a single chip, but in which the logical CPUs flexibly share some resources such as caches, buffers, functional units, etc.
Existing multi-core architectures also include clusters of CPUs, wherein each CPU of a given cluster is different from that of another cluster in terms of its function, architecture, configuration, and construction and therefore are not cache coherent. As such, CPU clusters use different addressing mechanisms, its not possible to implement a shared memory that can support both addressing means without translating message/request from each CPU or associated I/O device into a physical address that is understood at the main memory. At the same time, as CPUs from both the clusters need to be executed in parallel, mechanisms are needed to logically partition and share the main memory such that a virtualization technique can be implemented to translate CPU address to physical memory address. Some virtualization architectures fail to provide address translation mechanisms capable of supporting shared memory access in a heterogeneous environment. Certain solutions offer multi-core virtualization but suffer from assumptions that are made about the memory address map, such as the boot vector address, interrupt vector addresses, and Operating System (OS) entry points. Other solutions require different translation tables and configurations for memory access requests from the partitioned CPUs and I/O devices, which make such virtualization solutions complex and rigid.
In view of the foregoing, there is a need for a virtualization architecture that can support logical partitioning and virtualization for heterogeneous sets of CPU clusters.